1. Field of Invention
The present invention relates to a methods of fabricating a thin film transistor in which a metal silicide line generated from Metal Induced Lateral Crystallization is located at the outside of a channel region.
2. Discussion of Related Art
A polycrystalline silicon TFT (Thin Film Transistor) is used rather than an armophous silicon TFT for high resolution and fast operation speed in a liquid crystal display. The development of laser crystallization enables fabriction of; polysilicon TFT""s on a large-sized glass substrate under a temperature similar to a temperature in a process of fabricating armophous silicon TFT""S. However, the TFT fabricated by laser crystallization requires a long processing time and the related process equipments, causes difficulties in mass production.
Armophous silicon under a metal layer becomes crystallized by thermal treatment in MIC (Metal Induced Crystallization) after a specific metal layer has been formed on an armophous silicon layer. MIC enables low temperature crystallization and needs no equipments of high expenses. In spite of the merit of the low temperature crystallization, MIC causes metal contamination which deteriorates and changes the intrinsic characteristics of silicon due to the introduction of metal into the crystallized film.
A new crystallization method called Metal Induced Lateral Crystallization xe2x80x9cMILCxe2x80x9d[S. W. Lee and S. K. Joo, IEEE Electron Device Lett., 17(4), P.160, (1996)] has been proposed. MILC enables the crystallization of armophous silicon under a low temperature of about 400xc2x0 C. A crystallization of armophous silicon progresses laterally as the boundary of the silicon crystallized by MIC in MILC. Namely, the crystallization of silicon is induced laterally against the crystallization by MIC.
FIG. 1A to FIG. 1D show cross-sectional views of fabricating a TFT in which a silicon layer crystallized by MILC is used as a channel region.
Referring to FIG. 1A, an armophous silicon layer is deposited on an insulated substrate 100 on which a buffer layer has been formed. An active layer 10 is formed by patterning the armophous silicon layer by photolithography. A gate insulating layer 11 and a gate electrode 12 are formed on the active layer 10 by a conventional method.
Referring to FIG. 1B, a nickel film 13 having a thickness of 20 xc3x85 is deposited on the whole surface by sputtering. Accordingly, the portion of active layer on which the gate electrode 12 is not formed contacts the nickel film 13.
Referring to FIG. 1C, a region 10S and a drain region 10D which are doped heavily with impurity are formed in the active layer 10 by ion-implantation. A channel region 10C lies between the source 10S and the drain 10D.
Referring to FIG. 10D, the active layer of armophous silicon; 10 is crystallized by a thermal treatment of 300 to 500xc2x0 C. to the substrate 100 after the above step. Consequently, A portion of armophous silicon of the source 10S and drain 10D on which the nickel film has been formed is crystallized by MIC, while the other portion of armophous silicon where the channel 10C has been formed is crystallized by MILC.
FIG. 2A shows a TEM picture of a nickel-silicide line formed in the middle of the channel, and FIG. 2B shows a layout of a TFT after the crystalization by a conventional method wherein the arrows indicate the directions of crystallization by MILC. As shown in FIGS. 2A and 2B, an Ni-silicide line is formed in the middle of the channel region in the active layer. The thin Ni-silicide precipitates formed in the source and the drain crystallize silicon and move to the channel region. Accordingly, the Ni-silicide precipitates started to move from both ends of the source and the drain meet each other at the middle of the channel region, resulting in a Ni-silicide line. The Ni-silicide line becomes a defect deteriorating device characteristics, such as, the field effect mobility and the threshold voltage to lower the electrical characteristics of polysilicon TFT""S.
Accordingly, the present invention is directed to a method of fabricating a thin film transistor that substantially one or more of the problems due to limitations and disadvantages of the related art.
The object of the present invention is to provide a method of fabricating TFT which prevents the metal-silicide from being a defect in the channel region by means of locating the metal-silicide line outside the channel region.
Another object of the present invention is to provide a method of fabricating TFT which improves the characteristics of the TFT by means of crystallizing the semiconductor layer by MILC and simultaneously locating the metal-silicide lane generated therein outside the channel region.
Additional features and advantages of the invention will be set forth in the description which follows and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, the present invention includes the steps of forming a semiconductor layer on a substrate, said semiconductor layer having a first region, a channel region and a second region in order; forming a gate insulating layer and a gate electrode on said channel region; doping said first and said second region heavily with impurity; forming a metal film pattern making said first region a metal-offset; and crystallizing said semiconductor layer through thermal treatment of said semiconductor layer having said metal film.
Also, the present invention includes a method a thin film transistor comprising the steps of forming a semiconductor layer on a substrate, said semiconductor layer having a first region, a channel region and a second region in order, forming a gate insulating layer and a gate electrode on said channel region, forming a metal film pattern making said first region a metal-offset, doping said first and said second region heavily with impurity, and crystallizing said semiconductor layer through thermal treatment of said semiconductor layer having said metal film.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.